An embodiment of this invention relates generally to a semiconductor memory device and a method of operating the same and more particularly to a semiconductor memory device including memory cell blocks and a method of operating the same.
The memory cell array of semiconductor memory device such as a NAND flash memory device includes a plurality of memory cell blocks. Each of the memory cell blocks includes memory cells coupled to a plurality of word lines arranged between a drain select line and a source select line.
In order to store data in the memory cells, a program operation is sequentially performed from memory cells coupled to the first word line adjacent to the source select line, to memory cells coupled to the last word line adjacent to the drain select line. In this case, when the program operation is performed on memory cells coupled to a next word line after the program operation is performed on memory cells coupled to a previous word line, the threshold voltages of the memory cells coupled to the previous word line are shifted because the memory cells coupled to the previous word line are subject to a program interference phenomenon due to the program operation performed on memory cells coupled to a next word line. For this reason, data stored in the memory cells may be altered.
The program interference phenomenon becomes severe as the size of the memory cell is reduced or an interval between the word lines is narrowed with the efforts to highly integrate the semiconductor devices. Furthermore, a multi-level cell (MLC) in a NAND memory device in which data of multiple bits is stored in one memory cell, the threshold voltages of memory cells are shifted more severely owing to the program interference phenomenon, and thus data stored in the memory cells may be easily altered.
When a program operation is performed on memory cells coupled to a next word line, a program interference phenomenon generated in memory cells coupled to a previous word line needs to be inhibited or offset.
Several program operations of inhibiting the program interference phenomenon are being proposed. It is, however, difficult to inhibit the program interference phenomenon generated in the memory cells coupled to the previous word line because a program operation is performed on the memory cells coupled to the next word line after the program operation is performed on the memory cells coupled to the previous word line.